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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. july 2011 doc id 022018 rev 1 1/54 54 lsm330dl linear sensor module 3d accelerometer sensor and 3d gyroscope sensor features analog supply voltage 2.4 v to 3.6 v digital supply voltage i/os, 1.8v low-power mode power-down mode 3 independent acceleration channels and 3 angular rate channels 2 g /4 g /8 g /16 g dynamic, selectable full- scale acceleration range 250/500/2000 dps dynamic, selectable full- scale angular rate spi/i 2 c serial interface (16-bit data output) programmable interrupt generator for free-fall and motion detection ecopack ? , rohs, and ?green? compliant applications gps navigation systems impact recognition and logging gaming and virtual reality input devices motion-activated functions intelligent power saving for handheld devices vibration monitoring and compensation free-fall detection 6d-orientation detection description the lsm330dl is a system-in-package featuring a 3d digital accelerometer and a 3d digital gyroscope. st?s family of modules leverages a robust and mature manufacturing process already used for the production of micromachined accelerometers. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are based on cmos technology that allows designing a dedicated circuit which is trimmed to better match the sensing element characteristics. the lsm330dl has a dynamic, user-selectable full-scale acceleration range of 2 g /4 g /8 g /16 g and an angular rate of 250/500/2000 deg/sec. the accelerometer and gyroscope sensors can be either activated or put in low-power / power- down mode separately for power-saving optimized applications. the lsm330dl is available in a plastic land grid array (lga) package. several years ago st successfully pioneered the use of this package for accelerometers. today, st has the broadest manufa cturing capability in the world and unrivalled expertise for the production of sensors in a plastic lga package. llga 2 8 l 7.5 x 4.4 x 1.1 mm table 1. device summary part number temperature range [c] package packing lsm330dl -40 to +85 lga-28 tray LSM330DLTR -40 to +85 lga-28 tape & reel www.st.com
contents lsm330dl 2/54 doc id 022018 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 i2c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.2 zero level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
lsm330dl contents doc id 022018 rev 1 3/54 7 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 ctrl_reg1_a (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 ctrl_reg2_a (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 ctrl_reg3_a (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 ctrl_reg4_a (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.5 ctrl_reg5_a (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6 ctrl_reg6_a (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.7 reference/datacapture_a (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.8 status_reg_a (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.9 out_x_l_a (28h), out_x_h_a (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.10 out_y_l_a (2ah), out_y_h_a (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.11 out_z_l _a(2ch), out_z_h_a (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.12 fifo_ctrl_reg_a (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.13 fifo_src_reg_a (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.14 int1_cfg_a (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.15 int1_src_a (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.16 int1_ths_a (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.17 int1_duration_a (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.18 click_cfg _a (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19 click_src_a (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.20 click_ths_a (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.21 time_limit_a (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.22 time_latency_a (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.23 time window_a (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.24 ctrl_reg1_g (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.25 ctrl_reg2_g (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.26 ctrl_reg3_g (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.27 ctrl_reg4_g (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.28 ctrl_reg5_g (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.29 reference/datacapture_g (25h) . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.30 out_temp_g (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.31 status_reg_g (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.32 out_x_l_g (28h), out_x_h_g (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 44
contents lsm330dl 4/54 doc id 022018 rev 1 7.33 out_y_l_g (2ah), out_y_h_g (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.34 out_z_l_g (2ch), out_z_h_g (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.35 fifo_ctrl_reg_g (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.36 fifo_src_reg_g (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.37 int1_cfg_g (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.38 int1_src_g (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.39 int1_ths_xh_g (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.40 int1_ths_xl_g (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.41 int1_ths_yh_g (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.42 int1_ths_yl_g (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.43 int1_ths_zh_g (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.44 int1_ths_zl_g (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.45 int1_duration_g (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
lsm330dl list of tables doc id 022018 rev 1 5/54 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. serial interface terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 22 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22 table 16. linear acceleration sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17. angular rate sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 18. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. ctrl_reg1_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20. ctrl_reg1_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 21. data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 23. ctrl_reg2_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. ctrl_reg2_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 26. ctrl_reg3_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. ctrl_reg3_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 28. ctrl_reg4_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 29. ctrl_reg4_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 30. ctrl_reg5_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 31. ctrl_reg5_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 32. ctrl_reg6_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 33. ctrl_reg6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 34. reference/datacapture_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 35. reference/datacapture_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 36. status_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 37. status_reg_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 38. fifo_ctrl_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 39. fifo_ctrl_reg_a register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 40. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 41. fifo_src_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 42. int1_cfg_reg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 43. int1_cfg_reg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 table 44. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 45. int1_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 46. int1_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 47. int1_ths_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 48. int1_ths_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables lsm330dl 6/54 doc id 022018 rev 1 table 49. int1_duration_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 50. int1_duration_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 51. click_cfg_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 52. click_cfg_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 53. click_src_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 54. click_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 55. click_ths_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 56. click_src_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 57. time_limit_a register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 58. time_limit_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 59. time_latency_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 60. time_latency_a description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 61. time_window_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 62. time_window_a description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 63. ctrl_reg1_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 64. ctrl_reg1_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 65. dr and bw configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 66. power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 67. ctrl_reg2_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 68. ctrl_reg2_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 69. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 70. high-pass filter cutoff frequency configuration [hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 71. ctrl_reg3_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 72. ctrl_reg3_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 73. ctrl_reg4_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 74. ctrl_reg4_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 75. ctrl_reg5_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 76. ctrl_reg5_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 77. out_sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 78. int_sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 79. reference/datacapture_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 80. reference/datacapture_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 81. out_temp_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 82. out_temp_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 83. status_reg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 84. status_reg_g description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 85. fifo_ctrl_reg_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 86. fifo_ctrl_reg_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 87. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 88. fifo_src_reg_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 89. fifo_src_reg_g register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 90. int1_cfg_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 91. int1_cfg_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 92. int1_src_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 93. int1_src_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 94. int1_ths_xh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 95. int1_ths_xh_g description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 96. int1_ths_xl_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 97. int1_ths_xl_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 98. int1_ths_yh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 99. int1_ths_yh_g description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 100. int1_ths_yl_g register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
lsm330dl list of tables doc id 022018 rev 1 7/54 table 101. int1_ths_yl_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 102. int1_ths_zh_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 103. int1_ths_zh_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 104. int1_ths_zl_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 105. int1_ths_zl_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 106. int1_duration_g register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 107. int1_duration_g description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 table 108. llga 7.5 x 4.4 x 1.1 28l mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 109. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
list of figures lsm330dl 8/54 doc id 022018 rev 1 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. spi slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. i2c slave timing diagram (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. lsm330dl electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. int1_sel and out_sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 13. wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14. wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 15. llga 7.5 x 4.4 x 1.1 28l package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
lsm330dl block diagram and pin description doc id 022018 rev 1 9/54 1 block diagram and pin description 1.1 block diagram figure 1. block diagram y+ z+ y- z- x+ x- mux c s _a/g s da/ s di_a/g s do_a/g i ( a ) + - charge amplifier s en s ing block s en s ing interf a ce a/d control logic converter i2c/ s pi int1_a int2_a i ( ?) drive+ drive- feed ba ck+ feed ba ck- demodulator voltage automatic gain control low - pa ss filter gain amplifier analog conditioning control logic & interrupt gen. clock trimming circuit s reference s et/re s et circuit s generator pha s e + - charge amplifier y+ z+ y- z- x+ x- mux int1_g drdy_g/int2_g s cl_a/g am092 8 5v1
block diagram and pin description lsm330dl 10/54 doc id 022018 rev 1 1.2 pin description figure 2. pin connections y 1 x z direction of detectable acceleration s z direction of detectable angular rate 1 +? x +? z +? y y filtvdd filtin y (bottom view) 24 1 s do_a s da/ s di_g int1_a s da/ s di_a l s m 33 0dl re s 2 8 c s _g drdy_g/int2_g 10 15 11 14 25 int2_a s do_g re s vdd_io_a vcont re s re s vdd c s _a re s re s int1_g vdd re s re s s cl_a gnd re s s cl_g vdd_io_g re s x am09256v1 table 2. pin description pin# name function 1sda/sdi_a accelerometer: i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 2 res reserved, connect to gnd 3sdo_a accelerometer: spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 4scl_a accelerometer: i 2 c serial clock (scl) spi serial port clock (spc) 5 drdy_g/int2_g gyroscope data ready/interrupt signal 2 6 int1_a accelerometer interrupt signal 7sdo_g gyroscope: spi serial data output (sdo) i 2 c least significant bit of the device address (sa0) 8 int2_a accelerometer interrupt signal 9sda/sdi_g gyroscope: i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo)
lsm330dl block diagram and pin description doc id 022018 rev 1 11/54 10 cs_g gyroscope: spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 11 res reserved, connect to gnd 12 vdd_io_g gyroscope power supply for i/o pins 13 scl_g gyroscope: i 2 c serial clock (scl) spi serial port clock (spc) 14 res reserved connect to gnd 15 vdd power supply 16 res reserved, connect to gnd 17 cs_a accelerometer: spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 18 res reserved, connect to gnd 19 res reserved, connect to gnd 20 res reserved, connect to gnd 21 int1_g gyroscope interrupt signal 1 22 vdd power supply 23 res reserved, connect to gnd 24 res reserved, connect to gnd 25 gnd 0 v power supply 26 vcont pll filter connection 27 res reserved, connect to gnd 28 vdd_io_a accelerometer power supply for i/o pins table 2. pin description (continued) pin# name function
module specifications lsm330dl 12/54 doc id 022018 rev 1 2 module specifications 2.1 mechanical characteristics the values given in the following table are for the conditions vdd = 3 v, t = 25 c unless otherwise noted. (a) a. the product is factory calibrated at 3 v. the operat ional power supply range is from 2.4 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range (2) fs bit set to 00 2 g fs bit set to 01 4 fs bit set to 10 8 fs bit set to 11 16 g_fs angular rate measurement range (2) fs bit set to 00 250 dps fs bit set to 01 500 fs bit set to 10 2000 la_so linear acceleration sensitivity fs bit set to 00 1 m g /digit fs bit set to 01 2 fs bit set to 10 4 fs bit set to 11 12 g_so angular rate sensitivity fs bit set to 00 8.75 mdps/ digit fs bit set to 01 17.5 fs bit set to 10 70 la_so linear acceleration sensitivity change vs. temperature fs bit set to 00 0.05 %/c g_so angular rate sensitivity change vs. temp. from -40 to +85c 2 % la_tyoff typical zero- g level offset accuracy (3) fs bit set to 00 60 m g g_tyoff typical zero-rate level (4) fs bit set to 00 10 lsb la_tcoff zero- g level change vs. temperature max delta from 25 c 0.5 m g /c g_tcoff zero-rate level change vs. temperature fs bit set to 00 from -40 to +85c 0.03 dps/c an acceleration noise density fs bit set to 00, normal mode, odr bit set to 1001 220 g / rn rate noise density fs bit set to 00, bw = 50 hz 0.03 dps/ top operating temperature range -40 +85 c 1. typical specificat ions are not guaranteed. 2. verified by wafer level test and measur ement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning. 4. offset can be eliminated by enabl ing the built-in high-pass filter. h z h z
lsm330dl module specifications doc id 022018 rev 1 13/54 2.2 electrical characteristics the values given in the following table are for the conditions vdd = 3 v, t = 25 c unless otherwise noted. 2.3 temperature sensor characteristics the values given in the following table are for the conditions vdd = 3.0 v, t=25 c, unless otherwise noted. table 4. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 2.4 3.6 v vdd_io power supply for i/o 1.71 vdd+0.1 v la_idd la current consumption in normal mode odr = 50 hz 11 a odr = 1 hz 2 la_iddlowp la current consumption in low-power mode odr = 50 hz 6 a la_iddpdn la current consumption in power-down mode t = 25 c 0.5 a g_idd ar current consumption in normal mode 6.1 ma g_iddlowp ar supply current in sleep mode (2) 1.5 ma g_iddpdn ar current consumption in power-down mode t = 25 c 5 a vih digital high-level input voltage 0.8*vdd_io v vil digital low-level input voltage 0.2*vdd_io v voh high-level output voltage 0.9*vdd_io v vol low-level output voltage 0.1*vdd_io v top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. sleep mode introduces a faster turn- on time compared to power-down mode. table 5. temperature sensor characteristics (1) symbol parameter test condition min. typ. (2) max. unit tsdr temperature sensor output change vs. temperature - -1 c/digit todr temperature refresh rate 1 hz top operating temperature range -40 +85 c 1. the product is factory calibrated at 3.0 v. 2. typical specificat ions are not guaranteed.
module specifications lsm330dl 14/54 doc id 022018 rev 1 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface the values given in the following table are subject to the general operating conditions for vdd and t op . figure 3. spi slave timing diagram (b) 3. data on cs, spc, sdi and sdo concern the follow ing pins: cs_a/g, scl_a/g, sda/sdi_a/g, sdo_a/g table 6. spi slave timing values symbol parameter value (1) unit min max t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 6 ns t h(cs) cs hold time 8 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 9 t dis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock fr equency for spi with both 4 and 3 wires, based on characterization results, not tested in production. b. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in (3) (3) (3) (3) (3) (3) (3) (3)
lsm330dl module specifications doc id 022018 rev 1 15/54 2.4.2 i 2 c - inter-ic control interface the values given in the following table are subject to the general operating conditions for vdd and t op . figure 4. i 2 c slave timing diagram (3) 1. data based on standard i 2 c protocol requirement, not tested in production. 2 cb = total capacitance of one bus line, in pf 3. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 7. i 2 c slave timing values symbol parameter (1) i 2 c standard mode i 2 c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b ( 2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b ( 2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. scl (scl_a/g pin), sda (sda_a/g pin) sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start am092 38 v1
module specifications lsm330dl 16/54 doc id 022018 rev 1 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only a nd functional operation of the device under these conditions is not implied. ex posure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (scl_a/g, sda/sdi_a/g, sdo_a/g, cs_a/g) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 3 v) 3000 g for 0.5 ms 10000 g for 0.1 ms a unp acceleration (any axis, unpowered) 3000 g for 0.5 ms 10000 g for 0.1 ms t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this is a device sensitive to mechanical shock, improper handling can cause permanent damage to the part this is an esd-sensitive device, improper handling can cause permanent damage to the part
lsm330dl module specifications doc id 022018 rev 1 17/54 2.6 terminology 2.6.1 sensitivity linear acceleration sensitivity can be determined by applying 1 g acceleration to the device. as the sensor can measure dc accelerations, this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and then noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to th e actual sensitivity of the sensor. this value changes very little over temperature and also very little over time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. angular rate sensitivity describes the angular rate gain of the sensor and can be determined by applying a defined angular velocity to it. this value changes very little over temperature and also very little over time. 2.6.2 zero level linear acceleration zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no accelera tion is present. a sensor in a steady state on a horizontal surface will measure 0 g on the x-axis and 0 g on the y-axis whereas the z-axis will measure 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in th is case is called zero- g offset. offset is to some extent a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature? (refer to table 3 ). the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors. the angular rate zero-rate level describes the actual output value if there is no angular rate present. zero-rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can s lightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and also very little over time.
functionality lsm330dl 18/54 doc id 022018 rev 1 3 functionality the lsm330dl is a system-in-package featuring a 3d digital accelerometer and a 3d digital gyroscope. the complete device includes specific sensing elements and two ic interfaces able to measure both the acceleration and angular rate applied to the module and to provide a signal to the external world through an spi/i 2 c serial interface. the various sensing elements are manufactured using specialized micromachining processes, while the ic interfaces are based on cmos technology that allows designing a dedicated circuit which is trimmed to better match the sensing element characteristics. the lsm330dl may also be configured to generate an inertial wake-up and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. 3.1 factory calibration the ic interface is factory calibrated for sensit ivity and zero level. the trimming values are stored inside the device in non-volatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. this allows using the device without further calibration.
lsm330dl application hints doc id 022018 rev 1 19/54 4 application hints figure 5. lsm330dl electrical connections 4.1 external capacitors the device core is supplied through the vdd line. power supply decoupling capacitors (c4=100 nf ceramic, c3=10 f al) should be placed as near as possible to the supply pin of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). the functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the spi/i 2 c interface. table 9. part list component typical value c1 10 nf c2 470 nf c3 10 f c4 100 nf c5 r2 10 kohm digit a l s ign a l from/to s ign a l controller. s ign a l s level s a re defined b y proper s election of vdd y 1 x z direction of detectable acceleration s direction of detectable angular rate vdd_io gnd vdd c 3 c4 filtvdd filtin y (top view) 24 1 s do_a s da/ s di_g int1_a s da/ s di_a l s m 33 0dl re s 2 8 c s _g drdy_g 10 15 11 14 25 int2_a s do_g re s vdd_io_a vcont re s re s vdd c s _a re s re s int1_g vdd re s re s s cl_a gnd re s s cl_g vdd_io_g re s vdd_io c1 r2 c2 gnd c5 gnd re s erved pin s h a ve to b e connected to gnd z 1 + ? x + ? z + ? y y x am092 8 7v1
application hints lsm330dl 20/54 doc id 022018 rev 1 the functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user though the spi/i 2 c interface. 4.2 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standards. it is qualified for soldering heat resist ance according to jedec j-std-020d. leave ?pin 1 indicator? unconnected during soldering. the landing pattern and soldering recommendations are available at www.st.com/mems .
lsm330dl digital interfaces doc id 022018 rev 1 21/54 5 digital interfaces the registers embedded inside the lsm330dl may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 5.1 i 2 c serial interface the lsm330dl i 2 c is a bus slave. the i 2 c is employed to write data into the registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. table 10. serial interface pin description pin name pin description cs_a linear acceleration spi enable linear acceleration i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) cs_g angular rate spi enable angular rate i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl_a scl_g i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi_a sda/sdi_g i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo_a sdo_g i 2 c least significant bit of the device address (sa0) spi serial data output (sdo) table 11. serial interface terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
digital interfaces lsm330dl 22/54 doc id 022018 rev 1 5.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its own address. if they match, the device considers itself addressed by the master. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the lsm330dl behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been retu rned, an 8-bit sub-address (sub) will be transmitted: the 7 lsb represents the actual register address while the msb enables the address auto increment. if the msb of the sub field is ?1?, the sub (register address) will be automatically increased to allo w multiple data read/writes. data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait table 12. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak table 13. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 14. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
lsm330dl digital interfaces doc id 022018 rev 1 23/54 state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function), the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of first register to be read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. default address the sdo / sa0 pad can be used to modify the least significant bit of the device address. if the sa0 pad is connected to a voltage supply, lsb is ?1? (ex. address 0011001b), else if the sa0 pad is connected to ground, the lsb value is ?0? (ex address 0011000b). the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued afte r the two sub-address byte s. if the bit is ?0? (write), the master will tr ansmit to the slave with the direction unchanged. table 16 and table 17 explain how the sad+read/write bit pattern is composed, listing all the possible configurations. linear acceleration address: the default (factory) 7-bit slave address is 001100xb angular rate sensor: the default (factory) 7-bit slave address is 110100xb table 16. linear acceleration sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 001100 0 1 00110001 (31h) write 001100 0 0 00110000 (30h) read 001100 1 1 00110011 (33h) write 001100 1 0 00110010 (32h) table 17. angular rate sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 110100 0 1 11010001 (d1h) write 110100 0 0 11010000 (d0h) read 110100 1 1 11010011 (d3h) write 110100 1 0 11010010 (d2h)
digital interfaces lsm330dl 24/54 doc id 022018 rev 1 5.2 spi bus interface the lsm330dl spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo (spc, sdi, sd0 are common). figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are, respectively, the serial port data input and output. these lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multip le read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs, while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in th e latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain unch anged in multiple r ead/write commands. when 1, the address will be auto-incremented in multip le read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is the data that will be written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). in multiple read/write comman ds, further blocks of 8 clock periods will be added. when the ms bit is ?0?, the address used to read/write data remains the same for every block. when the ms bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7di6di5di4di3di2di1di0 do7do6do5do4do3do2do1do0 ms
lsm330dl digital interfaces doc id 022018 rev 1 25/54 5.2.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. the multiple byte read command is performed, adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, this bit does not increment the address. when 1, it increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reads. figure 8. multiple bytes spi read protocol (2 bytes example) 5.2.2 spi write figure 9. spi write protocol cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi sdo rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms
digital interfaces lsm330dl 26/54 doc id 022018 rev 1 the spi write command is performed with 16 clock pulses. the multiple byte write command is performed adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0, this bit does not increment the address, when 1, it increments the address in multiple writes. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is th e data that will be writ ten inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 10. multiple bytes spi write protocol (2 bytes example) 5.2.3 spi read in 3-wire mode the 3-wire mode is entered by setting to ?1? bit sim (spi serial interface mode selection) in ctrl_reg4. figure 11. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, this bit does not increment the address, when 1, it increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). the multiple read command is also available in 3-wire mode. cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
lsm330dl register mapping doc id 022018 rev 1 27/54 6 register mapping the table given below provides a listing of the 8-bit registers embedded in the device and their respective addresses. table 18. register address map name slave address type register address default comment hex binary reserved (do not modify) 001100xb 00 - 1f reserved ctrl_reg1_a 001100xb rw 20 010 0000 00000111 ctrl_reg2_a 001100xb rw 21 010 0001 00000000 ctrl_reg3_a 001100xb rw 22 010 0010 00000000 ctrl_reg4_a 001100xb rw 23 010 0011 00000000 ctrl_reg5_a 001100xb rw 24 010 0100 00000000 ctrl_reg6_a 001100xb rw 25 010 0101 00000000 reference/datacapture_a 001100xb rw 26 010 0110 00000000 status_reg_a 001100xb r 27 010 0111 00000000 out_x_l_a 001100xb r 28 010 1000 output out_x_h_a 001100xb r 29 010 1001 output out_y_l_a 001100xb r 2a 010 1010 output out_y_h_a 001100xb r 2b 010 1011 output out_z_l_a 001100xb r 2c 010 1100 output out_z_h_a 001100xb r 2d 010 1101 output fifo_ctrl_reg_a 001100xb rw 2e 010 1110 00000000 fifo_src_reg_a 001100xb r 2f 010 1111 int1_cfg_a 001100xb rw 30 011 0000 00000000 int1_src_a 001100xb r 31 011 0001 00000000 int1_ths_a 001100xb rw 32 011 0010 00000000 int1_duration_a 001100xb rw 33 011 0011 00000000 int2_cfg_a 001100xb rw 34 011 0100 00000000 int2_source_a 001100xb r 35 011 0101 00000000 int2_ths_a 001100xb rw 36 011 0110 00000000 int2_duration_a 001100xb rw 37 011 0111 00000000 click_cfg_a 001100xb rw 38 011 1000 00000000 click_src_a 001100xb rw 39 011 1001 00000000 click_ths_a 001100xb rw 3a 011 1010 00000000 time_limit_a 001100xb rw 3b 011 1011 00000000
register mapping lsm330dl 28/54 doc id 022018 rev 1 registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory-calibrated values. their content is automatically restored when the device is powered up. time_latency_a 001100xb rw 3c 011 1100 00000000 time_window_a 001100xb rw 3d 011 1101 00000000 reserved (do not modify) 001100xb 3e-3f reserved reserved 110100xb - 00-1e - - reserved ctrl_reg1_g 110100xb rw 20 010 0000 00000111 ctrl_reg2_g 110100xb rw 21 010 0001 00000000 ctrl_reg3_g 110100xb rw 22 010 0010 00000000 ctrl_reg4_g 110100xb rw 23 010 0011 00000000 ctrl_reg5_g 110100xb rw 24 010 0100 00000000 reference/datacapture_g 110100xb rw 25 010 0101 00000000 out_temp_g 110100xb r 26 010 0110 output status_reg_g 110100xb r 27 010 0111 output out_x_l_g 110100xb r 28 010 1000 output out_x_h_g 110100xb r 29 010 1001 output out_y_l_g 110100xb r 2a 010 1010 output out_y_h_g 110100xb r 2b 010 1011 output out_z_l_g 110100xb r 2c 010 1100 output out_z_h_g 110100xb r 2d 010 1101 output fifo_ctrl_reg_g 110100xb rw 2e 010 1110 00000000 fifo_src_reg_g 110100xb r 2f 010 1111 output int1_cfg_g 110100xb rw 30 011 0000 00000000 int1_src_g 110100xb r 31 011 0001 output int1_ths_xh_g 110100xb rw 32 011 0010 00000000 int1_ths_xl_g 110100xb rw 33 011 0011 00000000 int1_ths_yh_g 110100xb rw 34 011 0100 00000000 int1_ths_yl_g 110100xb rw 35 011 0101 00000000 int1_ths_zh_g 110100xb rw 36 011 0110 00000000 int1_ths_zl_g 110100xb rw 37 011 0111 00000000 int1_duration_g 110100xb rw 38 011 1000 00000000 table 18. register address map (continued) name slave address type register address default comment hex binary
lsm330dl registers description doc id 022018 rev 1 29/54 7 registers description the device contains a set of registers which are used to control its behavior and to retrieve acceleration, angular rate and temperature data. the register addresses, composed of 7 bits, are used to identify them and to write the data through the serial interface. 7.1 ctrl_reg1_a (20h) odr<3:0> is used to set power mode and odr selection. the following table gives the frequency for all combinations of odr<3:0>. table 19. ctrl_reg1_a register odr3 odr2 odr1 odr0 lpen zen yen xen table 20. ctrl_reg1_a description odr3-0 data rate selection. default value: 0 (0000: power-down; others: refer to table 21: data rate configuration lpen low-power mode enable. default value: 0 (0: normal mode, 1: low-power mode) zen z-axis enable. default value: 1 (0: z-axis disabled; 1: z-axis enabled) ye n y-axis enable. default value: 1 (0: y-axis disabled; 1: y-axis enabled) xen x-axis enable. default value: 1 (0: x-axis disabled; 1: x-axis enabled) table 21. data rate configuration odr3 odr2 odr1 odr0 power mode selection 0000power-down mode 0 0 0 1 normal / low-power mode (1 hz) 0 0 1 0 normal / low-power mode (10 hz) 0 0 1 1 normal / low-power mode (25 hz) 0 1 0 0 normal / low-power mode (50 hz) 0 1 0 1 normal / low-power mode (100 hz) 0 1 1 0 normal / low-power mode (200 hz) 0 1 1 1 normal / low-power mode (400 hz) 1000low-power mode (1.620 khz) 1 0 0 1 normal (1.344 khz) / low-power mode (5.376 khz)
registers description lsm330dl 30/54 doc id 022018 rev 1 7.2 ctrl_reg2_a (21h) table 22. operating mode selection operating mode ctrl_reg1[3] (lpen bit) ctrl_reg4[3] (hr bit) bw [hz] turn-on time [ms] low-power mode 1 0 odr/2 1 normal mode 0 1 odr/9 7/odr table 23. ctrl_reg2_a register hpm1 hpm0 hpcf2 hpcf1 fds hpclick hpis2 hpis1 table 24. ctrl_reg2_a description hpm1 -hpm0 high-pass filter mode selection. default value: 00 refer to table 25: high-pass filt er mode configuration hpcf2 - hpcf1 high-pass filter cutoff frequency selection fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from in ternal filter sent to output register and fifo) hpclick high-pass filter enabled for click function (0: filter bypassed; 1: filter enabled) hpis2 high-pass filter enabled for aoi function on interrupt 2, (0: filter bypassed; 1: filter enabled) hpis1 high-pass filter enabled for aoi function on interrupt 1, (0: filter bypassed; 1: filter enabled) table 25. high - pass filter mode configuration hpm1 hpm0 high - pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode 1 1 autoreset on interrupt event
lsm330dl registers description doc id 022018 rev 1 31/54 7.3 ctrl_reg3_a (22h) 7.4 ctrl_reg4_a (23h) table 26. ctrl_reg3_a register i1_click i1_aoi1 0 (1) 1. this bit has to be set ?0? for correct operation. i1_drdy1 i1_drdy2 i1_wtm i1_overrun -- table 27. ctrl_reg3_a description i1_click click interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_aoi1 aoi1 interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_drdy1 drdy1 interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_drdy2 drdy2 interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_wtm fifo watermark interrupt on int1_a. default value 0. (0: disable; 1: enable) i1_overrun fifo overrun interrupt on int1_a. default value 0. (0: disable; 1: enable) table 28. ctrl_reg4_a register bdu ble fs1 fs0 hr 0 (1) 0 (1) sim table 29. ctrl_reg4_a description bdu block data update. default value: 0(0: continuous update; 1: output registers not updated until msb and lsb reading) ble big/little endian data selection. default value 0. (0: data lsb at lower address; 1: data msb at lower address) fs1-fs0 full - scale selection. default value: 00 (00: +/- 2g; 01: +/- 4g; 10: +/- 8g; 11: +/- 16g) hr normal mode: default value: 0 (0: normal mode disable; 1: normal mode enable sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface)
registers description lsm330dl 32/54 doc id 022018 rev 1 7.5 ctrl_reg5_a (24h) 7.6 ctrl_reg6_a (25h) 7.7 reference/datacapture_a (26h) table 30. ctrl_reg5_a register boot fifo_en -- -- lir_int1 d4d_int1 0 (1) 1. this bit has to be set ?0? for correct operation. 0 (1) table 31. ctrl_reg5_a description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable) lir_int1 latch interrupt request on int1_s rc_a register, with int1_src_a register cleared by reading int1_src_a itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) d4d_int1 4d enable: 4d detection is enabled on int1_a when 6d bit on int1_cfg_a is set to 1. table 32. ctrl_reg6_a register i2_clicken i2_int1 0 (1) 1. this bit has to be set to ?0? for correct operation. boot_i2 0 (1) -- h_lactive -- table 33. ctrl_reg6 description i2_clicken click interrupt on int2_a. default value 0. i2_int1 interrupt 1 function enabled on int2_a. default 0. boot_i2 boot on int2_a. h_lactive 0: interrupt active high; 1: interrupt active low. table 34. reference/datacapture_a register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 35. reference/datacapture_a register description ref 7-ref0 reference value for interrupt generation. default value: 0
lsm330dl registers description doc id 022018 rev 1 33/54 7.8 status_reg_a (27h) 7.9 out_x_l_a (28h), out_x_h_a (29h) this register contains x-axis acceleration data. values are expressed in two?s complement. 7.10 out_y_l_a (2ah), out_y_h_a (2bh) this register containsy-axis acceleration data. values are expressed in two?s complement. 7.11 out_z_l _a(2ch), out_z_h_a (2dh) this register contains z-axis acceleration data. values are expressed in two?s complement. 7.12 fifo_ctrl_reg_a (2eh) table 36. status_reg_a register zyxor zor yor xor zyxda zda yda xda table 37. status_reg_a register description zyxor x-, y- and z-axis data overwrite. default value: 0 (0: no overwrite has occurred; 1: a new set of data has overwritten the previous ones) zor z-axis data overwrite. default value: 0 (0: no overrun has occurred; 1: a new data for the z-axis has overwritten the previous one) yor y-axis data overwrite. default value: 0 (0: no overwrite has occurred; 1: new data for the y-axis has overwritten the previous data) xor x-axis data overwrite. default value: 0 (0: no overwrite has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x-, y- and z-axis new data available. default value: 0 (0: a new set of data is not yet availabl e; 1: a new set of data is available) zda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) table 38. fifo_ctrl_reg_a register fm1 fm0 tr fth4 fth3 fth2 fth1 fth0
registers description lsm330dl 34/54 doc id 022018 rev 1 7.13 fifo_src_reg_a (2fh) 7.14 int1_cfg_a (30h) table 39. fifo_ctrl_reg_a register description fm1-fm0 fifo mode selection. default value: 00 (see table 40: fifo mode configuration ) tr trigger selection. default value: 0 0: trigger event linked to trigger signal on int1_a 1: trigger event linked to trigger signal on int2_a fth4:0 default value: 0 table 40. fifo mode configuration fm1 fm0 fifo mode 0 0 bypass mode 0 1 fifo mode 1 0 stream mode 1 1 trigger mode table 41. fifo_src_reg_a register wtm ovrn_fifo empty fss4 fss3 fss2 fss1 fss0 table 42. int1_cfg_reg_a register aoi 6d zhie/ zupe zlie/ zdowne yhie/ yupe ylie/ ydowne xhie/ xupe xlie/ xdowne table 43. int1_cfg_reg_a description aoi and/or combination of interrupt events. default value: 0. refer to table 44: interrupt mode 6d 6-direction detection function enabled. default value: 0. refer to table 44: interrupt mode zhie/ zupe enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie/ zdowne enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie/ yupe enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) ylie/ ydowne enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.)
lsm330dl registers description doc id 022018 rev 1 35/54 the contents of the int1_cfg_reg_a register are loaded at boot. a write operation at this address is possible only after system boot. the difference between aoi-6d = ?01? and aoi-6d = ?11? is defined as follows: aoi-6d = ?01? is movement recognition. an interrupt is generated when the orientation moves from an unknown zone to a known zone. the interrupt signal stays for a duration determined by odr. aoi-6d = ?11? is direction recognition. an interrupt is generated when the orientation is inside a known zone. the interrupt signal stays until orientation is inside the zone. 7.15 int1_src_a (31h) xhie/ xupe enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) xlie/xdo wne enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) table 44. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 116 - direction position recognition table 43. int1_cfg_reg_a description (continued) table 45. int1_src_a register 0 (1) 1. this bit has to be set to ?0? for correct operation. ia zh zl yh yl xh xl table 46. int1_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred)
registers description lsm330dl 36/54 doc id 022018 rev 1 the interrupt 1 source register is a read-only register. reading at this address clears the int1_src_a ia bit (and the interrupt signal on the int1_a pin) and allows the refreshment of data in the int1_src_a register if the latched option was chosen. 7.16 int1_ths_a (32h) 7.17 int1_duration_a (33h) the d6 - d0 bits set the minimum duration of the interrupt 1 event to be recognized. the duration of the steps and maximum values depend on the odr chosen. 7.18 click_cfg _a (38h) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 46. int1_src_a description table 47. int1_ths_a register 0 (1) 1. this bit has to be set to ?0? for correct operation. ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 48. int1_ths_a description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 49. int1_duration_a register 0 (1) 1. this bit has to be set to ?0? for correct operation. d6 d5 d4 d3 d2 d1 d0 table 50. int1_duration_a description d6 - d0 duration value. default value: 000 0000 table 51. click_cfg_a register -- -- zd zs yd ys xd xs
lsm330dl registers description doc id 022018 rev 1 37/54 7.19 click_src_a (39h) table 52. click_cfg_a description zd enable interrupt double click on z-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zs enable interrupt single click on z-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) yd enable interrupt double click on y-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ys enable interrupt single click on y-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xd enable interrupt double click on x-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xs enable interrupt single click on x-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) table 53. click_src_a register -- ia dclick sclick sign z y x table 54. click_src_a description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) dclick double click-click enable. default value: 0 (0: double click-click detection dis- able, 1: double click-click detection enable) sclick single click-click enable. default value: 0 (0: single click-click detection disable, 1: single click-click detection enable) sign click-click sign. 0: positive detection, 1: negative detection z z click-click detection. default value: 0 (0: no interrupt, 1: z high event has occurred) y y click-click detecti on. default value: 0 (0: no interrupt, 1: y high event has occurred) x x click-click detecti on. default value: 0 (0: no interrupt, 1: x high event has occurred)
registers description lsm330dl 38/54 doc id 022018 rev 1 7.20 click_ths_a (3ah) 7.21 time_limit_a (3bh) 7.22 time_latency_a (3ch) 7.23 time window_a (3dh) table 55. click_ths_a register lir ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 56. click_src_a description ths6-ths0 click-click threshold. default value: 000 0000 lir latch interrupt request for click-click function enable. 0 disable, 1 enable table 57. time_limit_a register -- tli6 tli5 tli4 tli3 tli2 tli1 tli0 table 58. time_limit_a description tli7-tli0 click-click time li mit. default value: 000 0000 table 59. time_latency_a register tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 table 60. time_latency_a description tla7-tla0 click-click time latency. default value: 000 0000 table 61. time_window_a register tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0 table 62. time_window_a description tw7-tw0 click-click time window
lsm330dl registers description doc id 022018 rev 1 39/54 7.24 ctrl_reg1_g (20h) dr<1:0> is used to set the odr selection. bw <1:0> is used to set bandwidth selection. the following table gives the frequencies for all combinations of the dr / bw bits. table 63. ctrl_reg1_g register dr1 dr0 bw1 bw0 pd zen yen xen table 64. ctrl_reg1_g description dr1-dr0 output data rate selection. refer to table 65: dr and bw configuration setting bw1-bw0 bandwidth selection. refer to table 65: dr and bw configuration setting pd power-down mode enable. default value: 0 (0: power-down mode, 1: normal mode or sleep mode) zen z-axis enable. default value: 1 (0: z-axis disabled; 1: z-axis enabled) yen y-axis enable. default value: 1 (0: y-axis disabled; 1: y-axis enabled) xen x-axis enable. default value: 1 (0: x-axis disabled; 1: x-axis enabled) table 65. dr and bw configuration setting dr <1:0> bw <1:0> odr [hz] cutoff [hz] 00 00 100 12.5 00 01 100 25 00 10 100 25 00 11 100 25 01 00 200 12.5 01 01 200 25 01 10 200 50 01 11 200 70 10 00 400 20 10 01 400 25 10 10 400 50 10 11 400 110 11 00 800 30 11 01 800 35 11 10 800 50 11 11 800 110
registers description lsm330dl 40/54 doc id 022018 rev 1 combination of pd, zen, yen, xen are used to set device in different modes (power - down / normal / sleep mode) according to the following table. 7.25 ctrl_reg2_g (21h) table 66. power mode selection configuration mode pd zen yen xen power-down 0 - - - sleep 1 0 0 0 normal 1 - - - table 67. ctrl_reg2_g register 0 (1) 1. this bit has to be set to ?0? for correct operation. 0 (1) hpm1 hpm1 hpcf3 hpcf2 hpcf1 hpcf0 table 68. ctrl_reg2_g description hpm1- hpm0 high-pass filter mode selection. default value: 00 refer to table 69: high-pass filter mode configuration hpcf3- hpcf0 high-pass filter cuto ff frequency selection refer to table 70: high-pass filter cutoff frequency configuration [hz] table 69. high - pass filter mode configuration hpm1 hpm0 high - pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode 1 1 autoreset on interrupt event table 70. high - pass filter cutoff frequency configuration [hz] hpcf3-0 odr = 100 hz odr = 200 hz odr = 400 hz odr = 800 hz 0000 8 15 30 56 0001 4 8 15 30 0010 2 4 8 15 0011 1 2 4 8 0100 0.5 1 2 4 0101 0.2 0.5 1 2
lsm330dl registers description doc id 022018 rev 1 41/54 7.26 ctrl_reg3_g (22h) 7.27 ctrl_reg4_g (23h) 0110 0.1 0.2 0.5 1 0111 0.05 0.1 0.2 0.5 1000 0.02 0.05 0.1 0.2 1001 0.01 0.02 0.05 0.1 table 70. high - pass filter cutoff frequency configuration [hz] (continued) hpcf3-0 odr = 100 hz odr = 200 hz odr = 400 hz odr = 800 hz table 71. ctrl_reg3_g register i1_int1 i1_boot h_lactive pp_od i2_drdy i2_wtm i2_orun i2_empty table 72. ctrl_reg3_g description i1_int1 interrupt enable on int1_g pin. default value 0. (0: disable; 1: enable) i1_boot boot status available on int1_g. de fault value 0. (0: disable; 1: enable) h_lactive interrupt active configuration on int1_g. default value 0. (0: high; 1:low) pp_od push-pull / open drain. default value: 0. (0: push-pull; 1: open drain) i2_drdy date ready on drdy_g/int2_g. default value 0. (0: disable; 1: enable) i2_wtm fifo watermark interrupt on drdy_g/int2_g. default value: 0. (0: disable; 1: enable) i2_orun fifo overrun interrupt on drdy_g/int2_g default value: 0. (0: disable; 1: enable) i2_empty fifo empty interrupt on drdy_g/int2_g. default value: 0. (0: disable; 1: enable) table 73. ctrl_reg4_g register bdu ble fs1 fs0 -- 0 (1) 1. this bit has to be set to ?0? for correct operation. 0 (1) sim table 74. ctrl_reg4_g description bdu block data update. default value: 0 (0: continuous update; 1: output regi sters not updated until msb and lsb have been read) ble big/little endian data selection. default value 0. (0: data lsb at lower address; 1: data msb at lower address)
registers description lsm330dl 42/54 doc id 022018 rev 1 7.28 ctrl_reg5_g (24h) figure 12. int1_sel and out_sel configuration block diagram fs1-fs0 full - scale selection. default value: 00 (00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface). table 74. ctrl_reg4_g description (continued) table 75. ctrl_reg5_g register boot fifo_en -- hpen int1_sel1 i nt1_sel0 out_sel1 out_sel0 table 76. ctrl_reg5_g description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable) hpen high-pass filter enable. default value: 0 (0: hpf disabled; 1: hpf enabled see figure 12: int1_sel and out_sel config- uration block diagram ) int1_sel1- int1_sel0 int1 selection configuration. default value: 0 (see figure 12: int1_sel and out_sel configuration block diagram ) out_sel1- out_sel1 out selection configuration. default value: 0 (see figure 12: int1_sel and out_sel configuration block diagram ) adc lpf1 hpf 0 1 hpen lpf2 10 11 01 00 o u t_ s el <1:0> d a t a reg fifo 3 2x16x 3 00 11 10 01 interr u pt gener a tor int1_ s el <1:0> am09276v1
lsm330dl registers description doc id 022018 rev 1 43/54 7.29 reference/datacapture_g (25h) 7.30 out_temp_g (26h) table 77. out_sel configuration setting hpen out_sel1 out_ sel0 description x00 data in datareg and fifo are non-high- pass-filtered x01 data in datareg and fifo are high-pass- filtered 01x data in datareg and fifo are low-pass- filtered by lpf2 11x data in datareg and fifo are high-pass and low-pass-filtered by lpf2 table 78. int_sel configuration setting hpen int_sel1 int_sel2 description x00 non-high-pass-filtered data are used for interrupt generation x01 high-pass-filtered data are used for interrupt generation 01x low-pass-filtered data are used for interrupt generation 11x high-pass and low-pass-filtered data are used for interrupt generation table 79. reference/datacapture_g register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 80. reference/datacapture_g register description ref 7-ref0 reference value for interrupt generation. default value: 0 table 81. out_temp_g register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0
registers description lsm330dl 44/54 doc id 022018 rev 1 7.31 status_reg_g (27h) 7.32 out_x_l_g (28h), out_x_h_g (29h) this register contains x-axis angular rate da ta. values are expressed as two?s complement. 7.33 out_y_l_g (2ah), out_y_h_g (2bh) this register contains y-axis angular rate data. values are expressed as two?s complement. 7.34 out_z_l_g (2ch), out_z_h_g (2dh) this register contains z-axis angular rate data. values are expressed as two?s complement. table 82. out_temp_g register description temp7-temp0 temperature data (1lsb/deg - 8 - bit resolution). the value is expressed as two?s complement. table 83. status_reg_g register zyxor zor yor xor zyxda zda yda xda table 84. status_reg_g description zyxor x-, y-, z-axis data overwrite. default value: 0 (0: no overwrite has occurred; 1: new data ha s overwritten the previous data before it was read) zor z-axis data overwrite. default value: 0 (0: no overwrite has occurred; 1: new data for the z-axis has overwritten the previous data) yor y-axis data overwrite. default value: 0 (0: no overwrite has occurred; 1: new data for the y-axis has overwritten the previous data) xor x-axis data overwrite. default value: 0 (0: no overwrite has occurred; 1: new data for the x-axis has overwritten the previous data) zyxda x-, y-, z-axis new data available. default value: 0 (0: a new set of data is not yet availabl e; 1: a new set of data is available) zda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet availabl e; 1: new data for the z-axis is available) yda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x-axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available)
lsm330dl registers description doc id 022018 rev 1 45/54 7.35 fifo_ctrl_reg_g (2eh) 7.36 fifo_src_reg_g (2fh) table 85. fifo_ctrl_reg_g register fm2 fm1 fm0 wtm4 wtm3 wtm2 wtm1 wtm0 table 86. fifo_ctrl_reg_g register description fm2-fm0 fifo mode selection. default value: 00 (see table 40: fifo mode configuration wtm4-wtm0 fifo threshold. watermark level setting table 87. fifo mode configuration fm2 fm1 fm0 fifo mode 000bypass mode 001fifo mode 010stream mode 011stream-to-fifo mode 100bypass-to-stream mode table 88. fifo_src_reg_g register wtm ovrn empty fss4 fss3 fss2 fss1 fss0 table 89. fifo_src_reg_g register description wtm watermark status. (0: fifo filling is lower than wtm level; 1: fifo filling is equal or higher than wtm level) ovrn overrun bit status. (0: fifo is not completely fille d; 1:fifo is completely filled) empty fifo empty bit. ( 0: fifo not empt y; 1: fifo empty) fss4-fss1 fifo stored data level
registers description lsm330dl 46/54 doc id 022018 rev 1 7.37 int1_cfg_g (30h) this is the configuration register for the interrupt source. table 90. int1_cfg_g register and/or lir zhie zlie yhie ylie xhie xlie table 91. int1_cfg_g description and/or and/or combination of interrupt events. default value: 0 (0: or combination of interrupt events 1: and combination of interrupt events lir latch interrupt request. default value: 0 (0: interrupt request not latched ; 1: interrupt request latched) cleared by reading int1_src_g reg. zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
lsm330dl registers description doc id 022018 rev 1 47/54 7.38 int1_src_g (31h) the interrupt source register is a read-only register. reading at this address clears the int1_src_g ia bit (and eventually the interrupt signal on the int1_g pin) and allows the refreshment of data in the int1_src_g register if the latched option was chosen. 7.39 int1_ths_xh_g (32h) 7.40 int1_ths_xl_g (33h) table 92. int1_src_g register 0 (1) 1. this bit has to be set to ?0? for correct operation. ia zh zl yh yl xh xl table 93. int1_src_g description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no in terrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 94. int1_ths_xh_g register -- thsx14 thsx13 thsx12 thsx11 thsx10 thsx9 thsx8 table 95. int1_ths_xh_g description thsx14 - thsx9 interrupt threshold. default value: 0000 0000 table 96. int1_ths_xl_g register thsx7 thsx6 thsx5 thsx4 thsx3 thsx2 thsx1 thsx0 table 97. int1_ths_xl_g description thsx7 - thsx0 interrupt threshold. default value: 0000 0000
registers description lsm330dl 48/54 doc id 022018 rev 1 7.41 int1_ths_yh_g (34h) 7.42 int1_ths_yl_g (35h) 7.43 int1_ths _zh_g (36h) 7.44 int1_ths_zl_g (37h) table 98. int1_ths_yh_g register -- thsy14 thsy13 thsy12 thsy11 thsy10 thsy9 thsy8 table 99. int1_ths_yh_g description thsy14 - thsy9 interrupt threshold. default value: 0000 0000 table 100. int1_ths_yl_g register thsr7 thsy6 thsy5 thsy4 thsy3 thsy2 thsy1 thsy0 table 101. int1_ths_yl_g description thsy7 - thsy0 interrupt threshold. default value: 0000 0000 table 102. int1_ths_zh_g register -- thsz14 thsz13 thsz12 thsz11 thsz10 thsz9 thsz8 table 103. int1_ths_zh_g description thsz14 - thsz9 interrupt threshold. default value: 0000 0000 table 104. int1_ths_zl_g register thsz7 thsz6 thsz5 thsz4 thsz3 thsz2 thsz1 thsz0 table 105. int1_ths_zl_g description thsz7 - thsz0 interrupt threshold. default value: 0000 0000
lsm330dl registers description doc id 022018 rev 1 49/54 7.45 int1_duration_g (38h) the d6 - d0 bits set the minimum duration of the interrupt event to be recognized. the duration of the steps and maximum values depend on the odr chosen. the wait bit has the following meaning: wait =?0?: the interrupt falls immediately if the signal crosses the selected threshold wait =?1?: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register. figure 13. wait disabled table 106. int1_duration_g register wait d6 d5 d4 d3 d2 d1 d0 table 107. int1_duration_g description wait wait enable. default value: 0 (0: disable; 1: enable) d6 - d0 duration value. default value: 000 0000
registers description lsm330dl 50/54 doc id 022018 rev 1 figure 14. wait enabled
lsm330dl package information doc id 022018 rev 1 51/54 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. ecopack ? specifications are available at: www.st.com .
package information lsm330dl 52/54 doc id 022018 rev 1 figure 15. llga 7.5 x 4.4 x 1.1 28l package drawing table 108. llga 7.5 x 4.4 x 1.1 28l mechanical data dim. mm min. typ. max. a1 1.100 a2 0.855 a3 0.200 d1 4.250 4.400 4.550 e1 7.350 7.500 7.650 n1 0.300 l1 5.400 l2 1.800 p2 1.200 t1 0.600 t2 0.400 m 0.100 d 0.3 k 0.050 h 0.100 d 1 e1 a1 p 2 l1 t2 t1 l 2 d m b e d a ? k ? k d ? k e ? k ? h c c pin 1 indicator top view seating plane n1 == a3 a2 ? k 8 190050_b
lsm330dl revision history doc id 022018 rev 1 53/54 9 revision history table 109. document revision history date revision changes 19-jul-2011 1 first release.
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